The ever-increasing demand of higher bandwidth switching chips forces earlier adoption of the latest technology nodes (e.g., ≤7 nm). Monolithic die solutions require that a serializer/deserializer (SerDes), a key element of all switching ASICs, must be available on the same technology nodes as the core logic. A solution that breaks the dependency on SerDes availability on a same technology node as a high-bandwidth switching chip ASIC needs to be developed.